For 15+ years, we have provided high-end Integrated Circuit layout services (also known as IC mask layout design), as part of our wider chip design services. Our analog IC layout services enable the physical design of the circuit to minimize the effects of technological process imperfections, provide the required circuit functionality, and fulfil the factory criteria.

Our engineering teams work with all major Integrated Device Manufacturer (IDM) and foundries, with wide IC technology expertise in bulk CMOS, BCD, SOI and FinFET technologies, process nodes from 500 nm down to 10 nm and below.

We work on all levels of custom IC layout from parameterized (p-cell) and standard cells, IO and ESD cells to block level, module and top – chip level layout.

KNOW-HOW

• Working with all major IDMs and foundries such as TSMC, GlobalFoundries – IBM, Xfab, TowerJazz – Panasonic, STM, TI, UMC, Dongbu, EM, NXP, AMS, Fujitsu, VIS.
• Wide IC technology expertise in bulk CMOS, BCD and SOI technologies, process nodes from 500 nm down to 10 nm.
• Experience with Deep Trench Isolation (DTI) technologies.
• Strong experience in power application layout, RF layout, precision base-band layout and ultra low power layout.
• Track record of on-time delivered high quality analog and mixed-signal IC layouts
• Ultra-low power/leakage layout design (ULP) – 16 bit microcontroller
• Wide variety of power management units (PMU) and modules
• High power amplifiers with 3A sourcing capabilities and 300W in a chip – audio amplifier
• Advanced high speed and high-resolution ADCs – 15bits, 20MS/s SAR ADC
• Performance critical and automotive circuits IC layout – Airbag monitoring, automotive communication interface
• RF layout with frequencies up to 60GHz – Bluetooth and WiFi transceivers, automotive radar

INTEGRATED CIRCUIT LAYOUT SERVICES

• Analog and mixed-signal custom IC layout design and physical verification
• Layout planned and developed as IP or full ASIC design
• Physical verification (DRC, LVS, ERC, antenna, density, EM, DFM…)
• IC layout parasitics extraction and its physical analysis and control
• IC layout methodology implementation and development
• Basic IC layout training courses
• External analog and digital IP modules integration and physical verification on chip
• Digital layout including floorplanning, P&R, physical verification, non-constrained
• Tape out support

DESIGN TOOLS

• Cadence Design Environment tools
  • Virtuoso VLE – VXL – GXL – VSE – VSR – VDI / Assura / QRC / EDI / PVS
• Mentor Graphics Calibre
  • nmDRC, nmLVS, PERC, PEX
• Data Management and Version Control
  • ClioSoft SOS, Enovia DesignSync, ICManage GDP

INTEGRATED CIRCUIT LAYOUT METHODOLOGIES

In order to produce a reliable integrated circuit with a high level of yield during fabrication and to obtain characteristics similar to those after the design and simulation of the system, it is necessary to have quality approach to the physical design.

The quality of analog integrated circuits largely depends on the physical design and production process.

This dependence is difficult to model and simulate in the early stages of development, so the layout of analog circuits is designed with full custom methodology where a layout engineer has absolute control over the position of each component on the chip and each connection.

• Using best matching techniques for sensitive analog circuits:
  • symmetrical and common-centroid layout, unit cells, orientation
  • dummy devices on sides or around matched array
  • routing control, parasitic capacitance and resistance control, shielding
  • strict local and global density control, dummy layer filling
• Multiple cut vias/contacts, guard-rings and good substrate tapping
• Area efficient rectangular, compact layout
• Following DFM rules (WPE, PSE, LOD effects), EM, antenna…
• Implementing ESD and latch-up protection
• Full triple well isolation, Deep Trench isolation, NT/BFMOAT, SOI
• Top metal power/ground star routing

CONTACT ELSYS AMERICA

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