In today’s complex integrated circuits or printed circuit boards require tools to help with the design and verification flows. Back in the early 80’s companies started to standardize software languages to help handle these complex designs. These hardware description languages help to compile to silicon automating what we used to do very manually. These tools are provided by international companies that provide software to evaluate designs in the semiconductor industry. We utilize these tools for:

• Design
• Analysis and Verification
• Emulation
• Manufacturing preparation (DFT)

VERIFICATION ENVIRONMENT ACCORDING TO UVM METHODOLOGY

• SystemVerilog verification environment
• Single verification environment for digital subsystem and SoC level mixed-signal Verification
• Analog modules written in Verilog AMS or SystemVerilog
• Cadence DMS library usage
• Top level netlist extraction using Cadence Virtuoso
• Make file creation or complete toolchain flow reuse
• Analog modules view control: simulations with models or with analog netlists for specific test scenarios

VERIFICATION TOOL

• Cadence AMS Designer

SIMULATION ENGINES

• Digital: Cadence Incisive
• Analog: Cadence Spectre or any other analog simulation engine

REVISION CONTROL SYSTEM

• DesignSync, Rational ClearCase