Open Position

Design Verification Engineer

Key Responsibilities / Duties:

  • verification methodology establishment
  • development of verification environment
  • developing test and functional coverage plans based on device specifications
  • analyzing and debugging simulation failures, as well as analyzing functional coverage results
  • verification progress tracking and close interaction with other teams in order to achieve product implementation milestones.

Qualification Requirements:

  • 2+ years of experience with verification methodologies – UVM, (Specman/eRM)
  • Background in digital electronics, ASIC/FPGA
  • Good knowledge of System Verilog/VHDL
  • Good Knowledge of processor architecture and Systems On Chip
  • Knowledge of C/C++
  • Knowledge of scripting tolls and languages is an advantage
  • Mobility is a plus
  • Highly motivated, well organized and team player
  • Good knowledge of English language


  • Integration program in a professional, young & dynamic team
  • Professional development opportunities
  • Competitive salaries & benefits
  • Compensation package includes also additional health insurance, sport & social activities
  • International work environment

You can find out more about our benefits here.

Growth empowered by passion and expertise. Employee satisfaction and loyalty are achievable only in environments where mutual understanding, respect, and trust exist. The mission of the HR department is to secure and further nurture these values.

Ivana Maričić
HR Manager

Apply for:
Design Verification Engineer