Senior Digital Design Verification

Senior Digital Design Verification
About us: 
ELSYS America is a leading engineering company specializing in the design of complex ASIC and SoCs.
From its technical center in the Bay Area, California, ELSYS America supports top-tier semiconductor corporations, as well as SMEs and startups.
Join the ELSYS Verification team to engage in intense verification of next generation of audio devices.

Reference: 
SR-DV
Job details: 
Responsibilities:
• Develop environments for complex system functional verification
• Debug both functional and environmental errors in the RTL or gate level, using simulation and debugging tools
• Develop automated functional verification regression infrastructure: design of checkers, monitors, and scoreboards

Location: 
Santa Clara
Profile: 
Desired qualifications:
Strong overall IP & SoC Verification experience
• 5+y of experience in verification using SystemVerilog language and UMV methodology
• Building and enhancing verification environments
• Practical experience driving ASIC level verification including test plan, test writing, RTL and Gate Level debugging, and strong knowledge of coverage-driven approach.

Preferred Qualifications:
• Verification of DSP systems, including frequency domain and FFT analysis
• Verification via System Verilog Assertions

Experience: 
Experienced
Skills: 
Digital IC
Contract: 
Contractor - 3 to 6 months with possible extension
Salary: 
Based on experience
Date: 
Wednesday, 11 October, 2017